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  <body><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><hr/><h1 class="register-section">CTIINTACK, CTI Output Trigger Acknowledge register</h1><p>The CTIINTACK characteristics are:</p><h2>Purpose</h2>
        <p>Can be used to deactivate the output triggers.</p>
      <h2>Configuration</h2><p>CTIINTACK is in the Debug power domain.
    </p><h2>Attributes</h2>
        <p>CTIINTACK is a 32-bit register.</p>
      <h2>Field descriptions</h2><table class="regdiagram"><thead><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td>24</td><td>23</td><td>22</td><td>21</td><td>20</td><td>19</td><td>18</td><td>17</td><td>16</td><td>15</td><td>14</td><td>13</td><td>12</td><td>11</td><td>10</td><td>9</td><td>8</td><td>7</td><td>6</td><td>5</td><td>4</td><td>3</td><td>2</td><td>1</td><td>0</td></tr></thead><tbody><tr class="firstrow"><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK31</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK30</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK29</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK28</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK27</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK26</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK25</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK24</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK23</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK22</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK21</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK20</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK19</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK18</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK17</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK16</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK15</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK14</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK13</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK12</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK11</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK10</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK9</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK8</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK7</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK6</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK5</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK4</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK3</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK2</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK1</a></td><td class="lr" colspan="1"><a href="#fieldset_0-31_0">ACK0</a></td></tr></tbody></table><h4 id="fieldset_0-31_0">ACK&lt;n&gt;, bit [n], for n = 31 to 0</h4><div class="field"><p>Acknowledge for output trigger &lt;n&gt;.</p>
<p>Bits [31:N] are RAZ/WI. N is the number of CTI triggers implemented as defined by the <a href="ext-ctidevid.html">CTIDEVID</a>.NUMTRIG field.</p>
<p>If any of the following is true, writes to ACK&lt;n&gt; are ignored:</p>
<ul>
<li>n &gt;= <a href="ext-ctidevid.html">CTIDEVID</a>.NUMTRIG, the number of implemented triggers.
</li><li>Output trigger n is not active.
</li><li>The channel mapping function output, as controlled by <a href="ext-ctioutenn.html">CTIOUTEN&lt;n&gt;</a>, is still active.
</li></ul>
<p>Otherwise, if any of the following are true, ACK&lt;n&gt; is <span class="arm-defined-word">RES0</span>:</p>
<ul>
<li>Output trigger n is not implemented.
</li><li>Output trigger n is not connected.
</li><li>Output trigger n is self-acknowledging and does not require software acknowledge.
</li></ul>
<p>Otherwise, the behavior on writes to ACK&lt;n&gt; is as follows:</p><table class="valuetable"><tr><th>ACK&lt;n&gt;</th><th>Meaning</th></tr><tr><td class="bitfield">0b0</td><td>
          <p>No effect</p>
        </td></tr><tr><td class="bitfield">0b1</td><td>
          <p>Deactivate the trigger.</p>
        </td></tr></table></div><h2>Accessing CTIINTACK</h2>
        <p>A debugger must read <a href="ext-ctitrigoutstatus.html">CTITRIGOUTSTATUS</a> to confirm that the output trigger has been acknowledged before generating any event that must be ordered after the write to CTIINTACK, such as a write to CTIAPPPULSE to activate another trigger.</p>
      <h4>CTIINTACK can be accessed through the external debug interface:</h4><table class="info"><tr><th>Component</th><th>Offset</th><th>Instance</th></tr><tr><td>CTI</td><td><span class="hexnumber">0x010</span></td><td>CTIINTACK</td></tr></table><p>This interface is accessible as follows:</p><ul><li>When SoftwareLockStatus(), accesses to this register are <span class="access_level">WI</span>.
          </li><li>When !SoftwareLockStatus(), accesses to this register are <span class="access_level">WO</span>.
          </li></ul><hr class="bottom_line"/><table style="margin: 0 auto;"><tr><td><div class="topbar"><a href="AArch32-regindex.html">AArch32 Registers</a></div></td><td><div class="topbar"><a href="AArch64-regindex.html">AArch64 Registers</a></div></td><td><div class="topbar"><a href="AArch32-sysindex.html">AArch32 Instructions</a></div></td><td><div class="topbar"><a href="AArch64-sysindex.html">AArch64 Instructions</a></div></td><td><div class="topbar"><a href="enc_index.html">Index by Encoding</a></div></td><td><div class="topbar"><a href="ext_alpha_index.html">External Registers</a></div></td><td><div class="topbar"><a href="ext_enc_index.html">External Registers by Offset</a></div></td><td><div class="topbar"><a href="func_index.html">Registers by Functional Group</a></div></td><td><div class="topbar"><a href="notice.html">Proprietary Notice</a></div></td></tr></table><p class="versions">30/03/2023 19:06; 997dd0cf3258cacf72aa7cf7a885f19a4758c3af</p><p class="copyconf">Copyright © 2010-2023 Arm Limited or its affiliates. All rights reserved. This document is Non-Confidential.</p></body>
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